1. Field of the Invention
This invention relates to a transistor having a scalable channel length and a method for making the same. By controlling the duration of an etch used to form the gate conductor, transistors having a desired channel length (e.g., less than 0.25 micron) may be accurately fabricated. In addition, the method described herein may be used to reproducibly fabricate a multiplicity of transistors having a desired channel length and to ensure consistency both across a semiconductor substrate and between wafers.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are patterned to form a gate conductor with source/drain regions (i.e., junctions) adjacent to and on opposite sides of the gate conductor within the substrate. The gate conductor and source/drain regions are then implanted with an impurity dopant. If the dopant species employed for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (n-channel) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (p-channel) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V.sub.T. Several factors contribute to V.sub.T, one of which is the effective channel length ("L.sub.eff ") of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. In VLSI designs, as the physical channel length decreases, so too must the L.sub.eff. Decreasing L.sub.eff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a shorter L.sub.eff. Accordingly, reducing the physical channel length, and hence the L.sub.eff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced L.sub.eff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies).
Unfortunately, minimizing the physical channel length of a transistor is somewhat limited by conventional techniques used to define the gate conductor of the transistor. As mentioned earlier, the gate conductor is typically formed from a polysilicon material. A technique known as lithography is used to pattern a photosensitive film (i.e., photoresist) above the polysilicon material. An optical image is transferred to the photoresist by projecting a form of radiation, typically ultraviolet light, through the transparent portions of a mask plate. The solubility of photoresist regions exposed to the radiation is altered by a photochemical reaction. The photoresist is washed with a solvent that preferentially removes resist areas of higher solubility. Those exposed portions of the polysilicon material not protected by photoresist are etched away, defining the geometric shape of a polysilicon gate conductor.
The lateral width (i.e., the distance between opposed sidewall surfaces) of the gate conductor, which dictates the physical channel length of a transistor, is thus defined by the lateral width of an overlying photoresist layer. The minimum lateral dimension that can be achieved for a patterned photoresist layer is unfortunately limited by, inter alia, the resolution of the optical system (i.e., aligner or printer) used to project the image onto the photoresist. The term "resolution" describes the ability of an optical system to distinguish closely spaced objects. Diffraction effects may undesirably occur as the radiation passes through slit-like transparent regions of the mask plate, scattering the radiation and therefore adversely affecting the resolution of the optical system. As such, the features patterned upon a masking plate may be skewed, enlarged, shortened, or otherwise incorrectly printed onto the photoresist.
In most core logic areas of an integrated circuit there are numerous logic gates, e.g., NAND and NOR gates, and interconnection between those gates. While reducing the L.sub.eff of each gate conductor within a logic gate increases the operational frequency and the integration density of an integrated circuit, other factors must also be manipulated to maximize circuit complexity and speed. For example, the spacing between series-connected transistors within a multiple-input logic gate must be decreased to provide for high packing density and high-speed operation of the logic gate. Unfortunately, the minimum definable dimension of lithography mandates the spacing between the gate conductors. The geometric shape of the gate conductors is generally defined by lithographically patterning photoresist over regions of a gate conductor material to be retained for the gate conductors. The minimum distance between portions of the photoresist patterned over the gate conductor material is limited by the constraints of lithography. Therefore, the lateral width of each region of the gate conductor material etched to form the gate conductors cannot be reduced below, e.g., 0.2 micron. As such, the minimum spacing between gate conductors within a logic gate is sacrificed by the conventional procedure of using lithography to pattern the gate conductors.
It would therefore be desirable to develop a transistor fabrication technique in which the channel length of the transistor is reduced to provide for high-frequency operation of an integrated circuit employing the transistor. More specifically, a process is needed in which the channel length is no longer dictated by the resolution of a lithography optical aligner. The lateral width of a gate conductor that defines the channel length of a transistor must no longer be determined by an image printed onto photoresist. Otherwise, the image could be altered during optical lithography, resulting in the dimensions of the gate conductor being altered from design specifications. A process which avoids the limitations of lithographic exposure used for defining opposed sidewall surfaces (i.e., boundaries) of conventional gate conductors would beneficially allow the channel length, and hence the L.sub.eff, of a transistor to be scaled with higher resolution and potentially to a smaller size. Minimizing and/or providing accurate control over L.sub.eff of a transistor would advantageously allow a designer to more closely design for specified operational parameters, such as speed at which the transistor switches between its on and off states.